AI與5G應用趨勢下，將加速3D異質整合在半導體業的發展。為了讓體積更小、效率提高，半導體晶片不斷整合再整合，從SoC到SiP，從2D平面到3D立體，以及近期熱門的Chiplet小晶片封裝。隨著倍數成長的高速運算需求，先進封裝技術，都以整合不同元件功能為目標。本課程內容說明因應Chiplet世代的3D異質整合，以及3D扇出型FOWLP/PLP整合製程。
3月22、23日(一)(二)09:30~16:30 授課講師：日本業界退役專家(語言：日文演說．逐步口譯)
3D Fan-Out integration and Panel Level Packaging (Process) to renovate device packaging ecosystem.
1. Revisiting fundamentals of fan-out wafer level packaging
1.1. Basic scheme of FOWLP process
a) Chip first/last and Face down/up classification
b) Reconstitution mold substrate
c) Materials properties to be required for FOWLP
1.2. Key points to note for FOWLP process integration
a) Die shift issues
b) Reliability issues
1.3. Manufacturing cost contribution
2. Through mold interconnect (TMI) process for 3D Fan-Out integration
2.1. InFO process and major difficulties in cost reduction
2.2. TMI process options
a) Electroplated tall Cu pillar
b) Vertical wire bonding
c) Laser drilling for via opening
d) Lithography process using photosensitive polymer mold
3. Fan-Out Panel Level Packaging/Process
3.1. Filling the gap of process level between panel and semiconductor chip
3.2. Challenges to build PLP mass production line
3.3. Development of PLP tools
3.4. Warpage issues on large panel forming
4. Building new ecosystem and R&D vector in future based on FOWLP/PLP
4.1. Memory modules and AI, 5G integration
a) Hybrid panel FO scheme for multi-chip stacked memory
b) Substrate free modules for high performance system with large scale memory
c) Bridge FO to replace Si interposer for higher flexibility of integration
4.2. Movement of industry reorganization between LCD and semiconductor
5．Closing
