因應AI、5G、HPC應用市場，半導體晶片的整合之路進入3D異質整合世代，透過RDL層串聯不同功能的晶片與被動元件。RDL在3D異質整合扮演重要角色，本課程將說明RDL重佈線技術在3D異質整合的情況。並以此解說，如何因應近期熱門的Chiplet彈性架構。
6月28、29日(一)(二)09:30~16:30 授課講師：日本業界專家(語言：日文演說．逐步口譯)
1. Introduction to Mid-end process technologies
1.1. Process gap of interconnect level between chip and package
1.2. Benefits to infuse front-end technologies into chip assembly process
1.3. Product values created by mid-end process technologies
2. 3D integrated device module
2.1. Stacking SoC with wide-band and large-scale memory
a) Logic-on-DRAM stacked device
b) HBM integration on Si interposer
c) Bridge chip integration
2.2. Fan-Out interconnect modules
a) InFO POP
b) 3D Fan-Out integration with through mold interconnects (TMI)
2.3. Chiplet integration
2.4. Direct stacked device based on Wafer-to Wafer and Chip-on-Wafer hybrid bonding
3. Fundamentals of interconnect process technologies
3.1. Process flow of RDL and micro-bumping
3.2. Challenges to realize more advanced RDL
3.3. TSV process scheme of via-middle and back-side-via
3.4. Key points to note for 3D chip stacking execution
a) Thermal stability of small volume solder bump joints
b) TSV stacking
4. What we understand when RDL is approaching LSI BEOL.
4.1. Basics understanding of metal interconnect reliability
4.2. Reliability issue due to the interface between Cu and organic dielectrics
4.3. Damascene process for organic dielectrics RDL
